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                how to write fast code - Module 2
              
            
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        <h3 id="M2-1"><a href="#M2-1" class="headerlink" title="M2-1"></a>M2-1</h3><h4 id="What-are-the-exploitable-levels-of-parallelism-in-a-multicore-processor"><a href="#What-are-the-exploitable-levels-of-parallelism-in-a-multicore-processor" class="headerlink" title="What are the exploitable levels of parallelism in a multicore processor?"></a>What are the exploitable levels of parallelism in a multicore processor?</h4><a id="more"></a>
<ul>
<li>SIMD-Level Parallelism: Exploited using vectorizing compiler and hand-core intrinsics</li>
<li>SMT-Level Parallelism: OS abstract it to core-level parallelism</li>
<li>Core-level Parallelism: Using threads to describe work sone on different cores</li>
</ul>
<h4 id="What-is-SPMD-And-how-to-use-OpenMP-to-do-SPMD"><a href="#What-is-SPMD-And-how-to-use-OpenMP-to-do-SPMD" class="headerlink" title="What is SPMD? And how to use OpenMP to do SPMD?"></a>What is SPMD? And how to use OpenMP to do SPMD?</h4><p>SPMD: Single Program Multiple Data (pragma omp for)</p>
<ul>
<li>Programmer must explicitly specify what each thread must do differently</li>
<li>The division of work is hard-core in the program</li>
<li>OpenMP: an API for shared memory multiprocessor.</li>
</ul>
<h4 id="What’s-the-difference-between-“critical”-and-“atomic”"><a href="#What’s-the-difference-between-“critical”-and-“atomic”" class="headerlink" title="What’s the difference between “critical” and “atomic”?"></a>What’s the difference between “critical” and “atomic”?</h4><ul>
<li>OpenMP critical: anything in a critical region, the OpenMP infrastructure will make sure it’s sequential. The enclosed block will be executed only one thread at a time and that’s simultaneously executed by multiple threads.</li>
<li>Atomic: only the memory update portion of the statement, the instruction will be performing atomically</li>
</ul>
<figure class="highlight plain"><table><tr><td class="gutter"><pre><div class="line">1</div><div class="line">2</div><div class="line">3</div><div class="line">4</div><div class="line">5</div><div class="line">6</div></pre></td><td class="code"><pre><div class="line">#pragma opm critical</div><div class="line">&#123;sum += 4.0/(1.0+x*x);&#125;</div><div class="line"></div><div class="line">tmp = 4.0/(1.0+x*x);</div><div class="line">#pragma omp atomic</div><div class="line">&#123;sum += tmp;&#125;</div></pre></td></tr></table></figure>
<h4 id="How-to-reduce-synchronization-cost-and-avoid-“false-sharing”"><a href="#How-to-reduce-synchronization-cost-and-avoid-“false-sharing”" class="headerlink" title="How to reduce synchronization cost and avoid “false sharing”?"></a>How to reduce synchronization cost and avoid “false sharing”?</h4><p>false sharing: if two threads are writing to the same cache line, conflicts occurs. Even if the adddress differs, one will still suffer performance penalty</p>
<p>Solution for False Sharing:(local_sum)</p>
<ul>
<li>Be aware of the cache line sizes for a platform</li>
<li>Avoid accessing the same cahce line from different threads</li>
</ul>
<figure class="highlight plain"><table><tr><td class="gutter"><pre><div class="line">1</div><div class="line">2</div><div class="line">3</div><div class="line">4</div><div class="line">5</div><div class="line">6</div><div class="line">7</div><div class="line">8</div><div class="line">9</div><div class="line">10</div><div class="line">11</div><div class="line">12</div><div class="line">13</div><div class="line">14</div></pre></td><td class="code"><pre><div class="line">//race condition:</div><div class="line">for(i=id,sum=0;i&lt;num_steps;i+=nthreads)&#123;</div><div class="line">	sum+=i;</div><div class="line">&#125;</div><div class="line">//false sharing:</div><div class="line">double sum[NUM_THREADS];</div><div class="line">for(i=id,sum[id]=0;i&lt;num_steps;i+=nthreads)&#123;</div><div class="line">	sum[id]+=i;</div><div class="line">&#125;</div><div class="line">// eliminate false sharing:</div><div class="line">double local_sum=0;</div><div class="line">for(i=id;i&lt;num_steps;i+=nthreads)&#123;</div><div class="line">	local_sum+=i;</div><div class="line">&#125;</div></pre></td></tr></table></figure>
<h4 id="What-are-the-scheduling-reduction-data-sharing-and-synchronization-options-for-OpenMP"><a href="#What-are-the-scheduling-reduction-data-sharing-and-synchronization-options-for-OpenMP" class="headerlink" title="What are the scheduling, reduction, data sharing, and synchronization options for OpenMP?"></a>What are the scheduling, reduction, data sharing, and synchronization options for OpenMP?</h4><ul>
<li><p>scheduling: The chedule clause affects how loop interations are mapped onto threads</p>
<ul>
<li>schedule(static[,chunk])</li>
<li>schedule(dynamic[,chunk])</li>
<li>schedule(guided[,chunk])</li>
<li>schedule(runtime)</li>
</ul>
</li>
<li><p>reduction(op: list)</p>
<ul>
<li>A local copy of each list variable is made and initialized depending on the “op”(eg. 0 for “+”)</li>
<li>Updates occur on the local copy</li>
<li>local copies are reduced into a single value and combined with tge original global value</li>
</ul>
</li>
<li><p>data sharing</p>
<ul>
<li>shared</li>
<li>private</li>
<li>firstprivate</li>
<li>lastprivate</li>
</ul>
</li>
<li><p>synchronization</p>
<ul>
<li>ordered: #pragma omp for order reduction(+:res); #pragma ordered</li>
<li>barrier: #pragma omp barrier; #pragma omp nowait</li>
<li>single: #pragma omp single</li>
</ul>
</li>
</ul>
<h4 id="How-is-this-relevant-to-writing-fast-code"><a href="#How-is-this-relevant-to-writing-fast-code" class="headerlink" title="How is this relevant to writing fast code?"></a>How is this relevant to writing fast code?</h4><p><img src="https://raw.githubusercontent.com/Annashuo/hello-world/master/M2-1.png" alt="module2-1"></p>
<h3 id="M2-2"><a href="#M2-2" class="headerlink" title="M2-2"></a>M2-2</h3><h4 id="Why-does-naïve-matrix-multiply-does-not-achieve-peak-performance-on-the-CPU"><a href="#Why-does-naïve-matrix-multiply-does-not-achieve-peak-performance-on-the-CPU" class="headerlink" title="Why does naïve matrix-multiply does not achieve peak performance on the CPU?"></a>Why does naïve matrix-multiply does not achieve peak performance on the CPU?</h4><p>Naive matrix-multiply is really no improvement over matrix vector multiply because for matrix vector multiply that’s exacly what our inner loop is we just repeat it back n times. The naive matrix-multiply does not achieve peak performance on the CPU is because of cache hierarchy. Page misses every iteration for large matrices.</p>
<h4 id="What-are-the-different-data-layouts-for-matrices"><a href="#What-are-the-different-data-layouts-for-matrices" class="headerlink" title="What are the different data layouts for matrices?"></a>What are the different data layouts for matrices?</h4><ul>
<li>Row major </li>
<li>Column major</li>
</ul>
<h4 id="Is-blocking-sufficient"><a href="#Is-blocking-sufficient" class="headerlink" title="Is blocking sufficient?"></a>Is blocking sufficient?</h4><ul>
<li>Block size adaptation for appropriate caches</li>
<li>Register-level blocking</li>
<li>Copy optimization(data layout)</li>
<li>Optimizing the mini-matrix-multiply(base case)</li>
<li>Multi-level blocking</li>
<li>Multi-level copying</li>
</ul>
<h4 id="What-can-be-learned-from-this-for-other-computations"><a href="#What-can-be-learned-from-this-for-other-computations" class="headerlink" title="What can be learned from this for other computations?"></a>What can be learned from this for other computations?</h4><ul>
<li>Strength reduction</li>
<li>Function inlining</li>
<li>Loop unrolling</li>
<li>Common subexpression elimination</li>
<li>Load/store elimination</li>
<li>Table lookups</li>
<li>Branch elimination</li>
</ul>
<h3 id="M2-3"><a href="#M2-3" class="headerlink" title="M2-3"></a>M2-3</h3><h4 id="What-is-the-roofline-model-What-are-the-metrics-and-axis-used"><a href="#What-is-the-roofline-model-What-are-the-metrics-and-axis-used" class="headerlink" title="What is the roofline model? What are the metrics and axis used?"></a>What is the roofline model? What are the metrics and axis used?</h4><p><strong>Roofline Model</strong>: Synthesize communication, computation, and locality into a single visually-intuitive performance figure using bound and bottleneck analysis.</p>
<p>On the x axis, we have the number of floating point operations per second divided by the bytes that we need to load from the DRAM. So, it’s a, a floating point divided by DRAM byte load ratio.</p>
<p>On the y axis, we have attainable giga flops per second. So, this is a peak amount of computation per second that one can do.</p>
<p>Attainable Performance=min{FLOP/s with Optimization, AI*Bandwidth with Optimizations}</p>
<p><strong>Arithmetic Intensity</strong>: the number of floating point operations to run the program, divided by, the number of bytes assessed, accessed from the main memory.</p>
<p><strong>floating point operations per second</strong>: floating point operations for a second with optimization, with the computation, through performance</p>
<ul>
<li><p>Computational Ceilings(in-core parallelism)</p>
<ul>
<li>If the code is dominated by adds or multiplies, then attainable performance is half of peak</li>
<li>If instructions aren’t SIMDized, attainable performance will be halved</li>
<li>If we don’t express 4-way ILP, performance will drop by as much as 4x</li>
</ul>
</li>
<li><p>Communication Ceilings(bandwidth)</p>
<ul>
<li>Explicit software prefetch instructions are required to achieve peak bandwidth</li>
<li>(NUMA) As such memory traffic must be correctly balanced among the two sockets to achieve good Stream bandwidth</li>
</ul>
</li>
<li><p>Locality Walls(Arithmetic Intensity = FLOPs/(Conflict+Capacity+Allocations+Compulsory))</p>
<ul>
<li>compulsory miss traffic</li>
<li>write allocation behavior</li>
<li>capacity miss traffic</li>
<li>conflict miss traffic</li>
</ul>
</li>
</ul>
<p><img src="https://raw.githubusercontent.com/Annashuo/hello-world/master/Roofline.png" alt="Roofline"> </p>
<p><img src="https://raw.githubusercontent.com/Annashuo/hello-world/master/Optimization_Categorization.png" alt="Optimization_Categorization"></p>
<h4 id="What’s-the-difference-between-”flop’s-per-memory-instruction”-from-“flop’s-per-DRAM-byte”"><a href="#What’s-the-difference-between-”flop’s-per-memory-instruction”-from-“flop’s-per-DRAM-byte”" class="headerlink" title="What’s the difference between:”flop’s per memory instruction” from “flop’s per DRAM byte”?"></a>What’s the difference between:”flop’s per memory instruction” from “flop’s per DRAM byte”?</h4><p>Memory Instructions: memory operations concurrently managed</p>
<p>True Arithmetic Intensity(AI)~Total Flops/Total DRAM Bytes</p>
<p>Where the memory instructions are an artifact of the code that you write. And the DRAM bytes is how that code is being mapped to a particular platform.</p>
<p>On the roofline model, what we see is the operating point initially, could be considered as at one particular flop per DRAM byte ratio. </p>
<ul>
<li><p>An example where the memory instructions is greater than the DRAM bytes: With the consideration of properties like write, allocate, traffic. We may have a lower number of floating point operations per DRAM bytes used.</p>
</li>
<li><p>An example where the DRAM bytes is greater than the memory instructions: Although we are executing a small number of memory instructions, they end up fetching a lot od data from memory because the data layout is not optimal for fetching data. And in order to fetch one memory instruction, we need to fetch a whole cache line from the DRAM to the cache hierarchy. </p>
</li>
</ul>
<h4 id="Consider-an-image-Image-height-width-If-one-were-to-stride-through-the-columns-of-values-what-would-be-the-effects-How-would-they-be-mapped-to-the-roofline"><a href="#Consider-an-image-Image-height-width-If-one-were-to-stride-through-the-columns-of-values-what-would-be-the-effects-How-would-they-be-mapped-to-the-roofline" class="headerlink" title="Consider an image Image[height][width]. If one were to stride through the columns of values, what would be the effects? How would they be mapped to the roofline?"></a>Consider an image Image[height][width]. If one were to stride through the columns of values, what would be the effects? How would they be mapped to the roofline?</h4><p>If one were to stride through the columns of values, it will cause compulsory misses and conflict misses, and will cause walls in roofline.</p>
<h4 id="How-does-one-model-incomplete-SIMDization-e-g-half-the-flop’s-can-be-SIMDized-insufficient-ILP-some-dependent-flop’s-or-an-imbalance-between-FPMUL’s-and-FPADD’s-on-the-roofline"><a href="#How-does-one-model-incomplete-SIMDization-e-g-half-the-flop’s-can-be-SIMDized-insufficient-ILP-some-dependent-flop’s-or-an-imbalance-between-FPMUL’s-and-FPADD’s-on-the-roofline" class="headerlink" title="How does one model incomplete SIMDization (e.g. half the flop’s can be SIMDized), insufficient ILP (some dependent flop’s), or an imbalance between FPMUL’s and FPADD’s on the roofline ?"></a>How does one model incomplete SIMDization (e.g. half the flop’s can be SIMDized), insufficient ILP (some dependent flop’s), or an imbalance between FPMUL’s and FPADD’s on the roofline ?</h4><p>If instructions aren’t SIMDized, attainable performance will be halved.</p>
<p>If we don’t express 4-way ILP, performance will drop by as much as 4x</p>
<p>If the code is dominated by adds, then attainable performance is half of peak</p>
<h4 id="How-would-one-model-branch-mispredicts-TLB-misses-or-too-many-streams-for-the-prefetchers-on-the-roofline"><a href="#How-would-one-model-branch-mispredicts-TLB-misses-or-too-many-streams-for-the-prefetchers-on-the-roofline" class="headerlink" title="How would one model {branch mispredicts, TLB misses, or too many streams for the prefetchers} on the roofline?"></a>How would one model {branch mispredicts, TLB misses, or too many streams for the prefetchers} on the roofline?</h4><p>Branch mispredicts, TLB misses or too many streams for the prefetchers will minimize the memory bandwidth, which limits the roofline.</p>
<p><img src="https://raw.githubusercontent.com/Annashuo/hello-world/master/roofline_mindmap.png" alt="Roofline"> </p>

      
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              <div class="post-toc-content"><ol class="nav"><li class="nav-item nav-level-3"><a class="nav-link" href="#M2-1"><span class="nav-number">1.</span> <span class="nav-text">M2-1</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#What-are-the-exploitable-levels-of-parallelism-in-a-multicore-processor"><span class="nav-number">1.1.</span> <span class="nav-text">What are the exploitable levels of parallelism in a multicore processor?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#What-is-SPMD-And-how-to-use-OpenMP-to-do-SPMD"><span class="nav-number">1.2.</span> <span class="nav-text">What is SPMD? And how to use OpenMP to do SPMD?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#What’s-the-difference-between-“critical”-and-“atomic”"><span class="nav-number">1.3.</span> <span class="nav-text">What’s the difference between “critical” and “atomic”?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#How-to-reduce-synchronization-cost-and-avoid-“false-sharing”"><span class="nav-number">1.4.</span> <span class="nav-text">How to reduce synchronization cost and avoid “false sharing”?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#What-are-the-scheduling-reduction-data-sharing-and-synchronization-options-for-OpenMP"><span class="nav-number">1.5.</span> <span class="nav-text">What are the scheduling, reduction, data sharing, and synchronization options for OpenMP?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#How-is-this-relevant-to-writing-fast-code"><span class="nav-number">1.6.</span> <span class="nav-text">How is this relevant to writing fast code?</span></a></li></ol></li><li class="nav-item nav-level-3"><a class="nav-link" href="#M2-2"><span class="nav-number">2.</span> <span class="nav-text">M2-2</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#Why-does-naïve-matrix-multiply-does-not-achieve-peak-performance-on-the-CPU"><span class="nav-number">2.1.</span> <span class="nav-text">Why does naïve matrix-multiply does not achieve peak performance on the CPU?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#What-are-the-different-data-layouts-for-matrices"><span class="nav-number">2.2.</span> <span class="nav-text">What are the different data layouts for matrices?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#Is-blocking-sufficient"><span class="nav-number">2.3.</span> <span class="nav-text">Is blocking sufficient?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#What-can-be-learned-from-this-for-other-computations"><span class="nav-number">2.4.</span> <span class="nav-text">What can be learned from this for other computations?</span></a></li></ol></li><li class="nav-item nav-level-3"><a class="nav-link" href="#M2-3"><span class="nav-number">3.</span> <span class="nav-text">M2-3</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#What-is-the-roofline-model-What-are-the-metrics-and-axis-used"><span class="nav-number">3.1.</span> <span class="nav-text">What is the roofline model? What are the metrics and axis used?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#What’s-the-difference-between-”flop’s-per-memory-instruction”-from-“flop’s-per-DRAM-byte”"><span class="nav-number">3.2.</span> <span class="nav-text">What’s the difference between:”flop’s per memory instruction” from “flop’s per DRAM byte”?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#Consider-an-image-Image-height-width-If-one-were-to-stride-through-the-columns-of-values-what-would-be-the-effects-How-would-they-be-mapped-to-the-roofline"><span class="nav-number">3.3.</span> <span class="nav-text">Consider an image Image[height][width]. If one were to stride through the columns of values, what would be the effects? How would they be mapped to the roofline?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#How-does-one-model-incomplete-SIMDization-e-g-half-the-flop’s-can-be-SIMDized-insufficient-ILP-some-dependent-flop’s-or-an-imbalance-between-FPMUL’s-and-FPADD’s-on-the-roofline"><span class="nav-number">3.4.</span> <span class="nav-text">How does one model incomplete SIMDization (e.g. half the flop’s can be SIMDized), insufficient ILP (some dependent flop’s), or an imbalance between FPMUL’s and FPADD’s on the roofline ?</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#How-would-one-model-branch-mispredicts-TLB-misses-or-too-many-streams-for-the-prefetchers-on-the-roofline"><span class="nav-number">3.5.</span> <span class="nav-text">How would one model {branch mispredicts, TLB misses, or too many streams for the prefetchers} on the roofline?</span></a></li></ol></li></ol></div>
            

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